Large scale integration (LSI) techniques have made possible the construction of memory devices having large arrays of binary storage elements formed on a single chip of silicon. The immediate advantages of such arrangements are high cell density and low power requirements. In the production of monolithic chips, it is not unusual for the yield of good chips from a silicon wafer to be low, especially during early production runs. For each perfect chip produced, there are a number of chips that are almost perfect, having one or more localized defects which render unusable a single cell, a few closely associated cells or clusters of cells.
It will be appreciated that the presence of only one defective cell in an otherwise perfect memory array ca render the entire memory inoperable.
As cell density increases, the likelihood of processing defects increases. Therefore, there is a continuing interest in techniques for improving the yield of memory arrays, and for repairing or otherwise rendering usable those memory arrays having processing defects.